DIGITAL BASEBAND TRANSMITTER/RECEIVER ON A DIGITAL SIGNAL PROCESSOR

    This project is design based on the paper "Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor". The block diagram of a digital baseband transmitter defined in the 802.11a standard is shown in Figure. The input bit stream is first randomized by a scrambler and encoded by a convolutional encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. 16-QAM,64-QAM, BPSK, QPSK  modulation schemes are used in the design. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally, the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol. Watch the simulation video demo for design working process.

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SIMULATION VIDEO DEMO                                                                                                                                     


You can DOWNLOAD the Matlab code to understand the concept. Looking for full design, contact +91 7904568456 by whatsapp or sales@verilogcourseteam.com, fee applicable.

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