Phase-locked loops (PLLs) are most common in applications like wireless transceivers, cellular phones, global positioning systems, etc. An important characteristic of a PLL is its lock time. Lock time is the time a PLL takes to adapt and settle down to changes in the input frequency. Conventional PLLs employ the technique of phase tracking which takes a long time to lock, so they are misfits for contemporary high-speed high-throughput technology. Fast locking is required for fast-frequency hopping among data bursts in high-speed digital communications PLLs with low-power constraints demand that they are turned off during inactivity but lock quickly when turned back on.Fast locking is, therefore, a necessity for spread-spectrum communications, cellular phones, clock/data recovery circuits, etc.
    A novel successive-approximation fast-locking Digital Phase Lock Loop (SAR DPLL) is presented and modeled using Matlab. The DPLL operation includes two stages: (1) a novel course-tuning stage that employs a successive-approximation algorithm which is similar to the algorithm employed in SAR Analog-to-Digital converters (ADCs) and (2) A fine-tuning stage which is similar to conventional DPLLs.The coarse-tuning stage includes a frequency comparator, a successive-approximation register, a digital-to-analog converter (DAC), and control logic.

Reference Paper: A Novel Successive-Approximation Fast-Locking Digital Phase-Locked Loop
Author’s Name:  Mahmoud Fawzy Wagdy and Anurag Nannaka
Source: Department of Electrical Engineering, California State University
Year: Unknown
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