Terms and Conditions

1.Verilog Course Team reserves all copyrights of the source codes and design.
2.We request candidate to furnish the correct details in the Request Form,if it found as fake,necessary action will be taken without any Prior notice in order to safeguard the data piracy.
3.Verilog Course Team have rights to communicate with the Professor/University for verification. 
4.Project/Source Code and Documents should be used only for reference,not for Academic Thesis/Research Work (PhD)/Commercial and Verilog Course Team owns the copyrights.
5.Candidate should produce the scanned ID Card Copy.
6.Read the Home page to know more details about Verilog Course Team.