Terms and Conditions


1. Verilog Course Team reserves all copyrights of the source codes/design.
2. We request the candidate to furnish the correct details in the Request Form, if it found as fake, there won't be any response.
3. Verilog Course Team has rights to communicate with the Professor/University for verification. 
4. Project/Source Code and documents should be used only for reference, not for Research Work (Ph.D.)/Commercial.
5. Candidate should produce the scanned ID Card Copy.
6. Read the Home page to know more details about Verilog Course Team.