• Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
  • A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
  • A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
  • FPGA Implementations of the Hummingbird Cryptographic Algorithm
  • FPGA Implementation(s) of a Scalable Encryption Algorithm
  • A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
  • Contrast Enhancement of Color Images using Tunable Sigmoid Function
  • Image Compression with Different Types of Wavelets
  • Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms using Xilinx System Generator.
  • Design and FPGA Implementation of Modular Multiplication methods using Cellular Automata
  • Image Edge Detection Based on FPGA
  • VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN
  • Improvisation of Gabor Filter design using Verilog HDL
  • Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
  • A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
  • VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for JPEG
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