2011 TOPICS
- An Efficient Implementation of Floating Point Multiplier
- High Speed and Low Space Complexity FPGA Based ECC Processor
- A blind digital watermarking algorithm based on wavelet transform
- A Distributed Canny Edge Detector And Its Implementation on FPGA
- Design and Simulation of UART Serial Communication Module Based on VHDL
- Design and VLSI implementation of high-performance face-detection engine for mobile applications
- Design and Implementation of Area-optimized AES based on FPGA
- Design of Low Power And High Speed Configurable Booth Multiplier
- Face detection and recognition method based on skin color and depth information
- High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
- A New Reversible Design of BCD Adder
- Digital Image Authentication from JPEG Headers
- Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
- Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
- A Very Fast and Low Power Carry Select Adder Circuit
- A_multichannel watermaking scheme based on DCT-DWT
- An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
- Design and Characterization of Parallel Prefix Adders using FPGAs
- FPGA based FFT Algorithm Implementation in WiMAX Communications System
- FPGA Design of AES Core Architecture for Portable Hard Disk
- FPGA Implementation of RS232 to Universal serial bus converter
- Image Encryption Based On AES Key Expansion
- Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
- An Efficient Architecture Design for VGA Monitor Controller
- Curve Fitting Algorithm FPGA implementation
- FPGA Implementation of AES Algorithm
- Design of Low Power Column Bypass Multiplier using FPGA
- Design of Serial Communication Interface Based on FPGA
- Design and Implementation of an FPGA-based Real-Time Face Recognition System
- VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders
- Low Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
- Design of Low Power And High Speed Configurable Booth Multiplier
- Design Enhancement Of combinational Neural Networks using HDL Based FPGA framework for Pattern Recognition
- Efficient VLSI Architecture for Discrete Wavelet Transform
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