• Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits
  • Design of Low Power High Speed VLSI Adder Subsystem
  • Synthesis and Implementation of UART using VHDL Codes
  • HICPA: A Hybrid Low Power Adder for High-Performance Processors
  • Low-Power and Area-Efficient Carry Select Adder
  • Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
  • Design and Implementation of a High Performance Multiplier using HDL
  • Design of Low-Power and High Performance Radix-4 Multiplier
  • Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
  • FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers
  • High Speed and Area Efficient Vedic Multiplier
  • High speed Modified Booth Encoder multiplier for signed and unsigned numbers
  • An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
  • High Speed Signed Multiplier for Digital Signal Processing Applications
  • Accumulator Based 3-Weight Pattern Generation
  • Design of Low Power TPG Using LP-LFSR
  • Viterbi-Based Efficient Test Data Compression
  • A Feature-Based Robust Digital Image Watermarking Scheme
  • Digital Image Watermarking Based on Super Resolution Image Reconstruction
  • Hardware Implementation of a Digital Watermarking System for Video Authentication
  • Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code
  • Watermarking Scheme for Copyright Protection of 3d Animated Model
  • Efficiency of BCH Codes in Digital Image Watermarking
  • Image Magnification by Modifying DCT Coefficients
  • A Real-time Face Detection And Recognition System
  • VHDL Implementation of UART with Status Register
  • Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC
  • FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
  • Pipelined Parallel FFT Architectures via Folding Transformation
  • VHDL Design for Image Segmentation using Gabor filter for Disease Detection.
  • An Efficient Viterbi Decoder
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • Very Low Resolution Face Recognition Problem
  • Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
                                                                                             2011 Topics