• Distributed Canny Edge Detector Algorithm and FPGA Implementation
  • Area-Delay-Power Efficient Carry-Select Adder
  • Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
  • Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
  • Area-Delay Efficient Binary Adders in QCA
  • Efficient Integer DCT Architectures for HEVC
  • Recursive Approach to the Design of a Parallel Self-Timed Adder
  • Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
  • High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
  • Comments on Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding
  • Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform
  • A Decimal  Binary Multi-operand Adder using a Fast Binary to Decimal Converter
  • ASIC Design of Reversible Multiplier Circuit
  • A Novel MRI Brain Edge Detection Using PSOFCM Segmentation and Canny Algorithm
  • Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder
  • Real Time Human Face Detection and Tracking
  • Key Dependent Image Steganography Using Edge Detection
  • High-Throughput Programmable Systolic Array FFT Architecture and FPGA Implementations
  • VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications
  • Area–Delay–Power Efficient Carry-Select Adder
  • Design of Low Power Split Path Data Driven Dynamic Ripple Carry Adders
  • A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL
  • Pipelined Architecture for Vedic Multiplier
  • Block Based Robust Blind Image Watermarking Using Discrete Wavelet Transform
  • Gabor Filter Based Hand-Drawn Underline Removal in Printed Documents
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