• Reviewing High-Radix Signed-Digit Adders
  • A New-High Speed-Low Power-Carry Select adder Using Modified GDI
  • Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
  • A Modified Partial Product Generator for Redundant Binary Multipliers
  • A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
  • Design and Analysis of Approximate Compressors for Multiplication
  • Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  • Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
  • Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
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