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2016 TOPICS
- A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
- A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
- A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT
- High-Speed and Low-Latency ECC Processor Implementation Over GF(2m)on FPGA
- Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
- LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
- Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
- On Efficient Retiming of Fixed-Point Circuits
- Hybrid LUT/Multiplexer FPGA Logic Architectures
- Concept, Design, and Implementation of Reconfigurable CORDIC
- Computing Seeds for LFSR-Based Test Generation From Nontest CubesReviewing High-Radix Signed-Digit Adders
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