FPGA BASED DESIGN OF A NOVEL ENHANCED ERROR DETECTION AND CORRECTION TECHNIQUE
Abstract—With the increase of data transmission and hence
sources of noise and interference, engineers have been struggling
with the demand for more efficient and reliable techniques for
detecting and correcting errors in received data. Although
several techniques and approaches have been proposed and
applied in the last decade, data reliability in transmission is still a
problem. In this paper we propose a high efficient combined
error detection and correction technique based on the
Orthogonal Codes Convolution, Closest Match, and vertical
parity. This method has been experimentally implemented and
simulated using Field Programmable Gate Array (FPGA).
Simulation results show that the proposed technique detects
99.99% of the errors and corrects as predicted up to (n/2-1) bits
of errors in the received impaired n-bit code.
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A HIGH-SPEED 32-BIT SIGNED/UNSIGNED PIPELINED MULTIPLIER
Abstract—In this paper, a novel unified implementation of
signed/unsigned multiplication is proposed using a simple signcontrol
unit together with a line of multiplexers. The proposed
approach is demonstrated through a 0.18μm CMOS implementation
of a 32-bit signed/unsigned multiplier. Reported results
show that the proposed unified signed/unsigned implementation
is very compact with only 0.45% silicon area overhead. The
critical path delay of the proposed multiplier is about 3.13ns.
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