LOW POWER MULTIPLIER USING RADIX-2 BOOTH MULTIPLIER

    This project is design based on the paper "A Low-Power Multiplier With the Spurious Power Suppression Technique". This project is designed based on the spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. The SPST has been applied to both the Radix-2 Booth decoder and the compression tree of multipliers to enlarge the power reduction. The project is developed using Verilog HDL and simulated using Modelsim Software. Watch the simulation video demo for design working process.

Block diagram low-power SPST-equipped multiplier


Request source code for academic purpose REQUEST FORM

SIMULATION VIDEO DEMO          

                                                                                                                          


You can DOWNLOAD the sample code for Radix-2 booth encoder. Need design files, contact sales@verilogcourseteam.com or whatsapp @

+91 7904568456, fee applicable.

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