This project is based on a 9/7 lifting DWT algorithm with a multi-stage pipeline structure. The lifting-based DWT scheme presents many advantages over the convolution-based approach such as computational efficiency, saving of memory, "in-place" computation of the DWT, integer-to-integer wavelet transform (IWT), symmetric forward and inverse transform, etc. The main feature of the lifting-based discrete wavelet transform scheme is to break up the high-pass and low-pass wavelet filters into a sequence of smaller filters that in turn can be converted into a sequence of upper and lower triangular matrices. The basic idea behind the lifting scheme is to use data correlation to remove the redundancy. The lifting algorithm can be computed in three main phases, namely: the split phase, the predict phase, and the update phase. The design is developed using Verilog HDL with Matlab program and testes using Matlab and Modelsim Software. The simulation procedure is shown in the below video demo. The design is compared with Synthesis results using Xilinx ISE.

Device Utilization Summary-Non Pipeline DWT

Device Utilization Summary-Pipeline DWT

Reference Paper: Pipelined Architecture for FPGA Implementation of Lifting-Based DWT
Author’s Name: Zhigang WU and Wei WANG
Source: IEEE

Request source code for academic purpose REQUEST FORM or contact +91 7904568456 by whatsapp or sales@verilogcourseteam.com, fee applicable.

SIMULATION VIDEO DEMO