CONVOLUTION ALGORITHM USING VEDIC MULTIPIER

    This project is design based on the paper "High Speed Convolution and Deconvolution Algorithm".In Digital Signal Processing, the convolution and deconvolution with a very long sequence is ubiquitous in many application areas. This project presents a direct method of computing the convolution with AWGN noise removal application. The approach is easy to learn because of the similarities to computing the multiplication of two numbers. The most significant aspect of the proposed method is the development of a multiplier architecture based on Ancient Indian Vedic Mathematics sutras Urdhvatriyagbhyam algorithm.

Convolution method

You can DOWNLOAD 8 bit Veridc Multiplier Verilog HDL code and reference document.Looking for full design contact us sales@verilogcourseteam.com

SIMULATION VIDEO DEMO          

                                                                                                                          


PREVIOUS PAGE|NEXT PAGE