This project is design based on the paper "Improved Architectures for a Fused FloatingPoint AddSubtract Unit".The fused floatingpoint addsubtract unit is useful for digital signal processing (DSP) applications such as fast Fourier transform (FFT) and discrete cosine transform (DCT) butterfly operations. To improve the performance of the fused floatingpoint addsubtract unit, a dualpath algorithm and pipelining are employed. The proposed designs are implemented for both single and double precision. This project is designed using Verilog HDL and simulated using Modelsim for the below methods.
 Fused floatingpoint addsubtract unit
 Dualpath fused floatingpoint addsubtract unit
 Fused floatingpoint addsubtract unit (after Close path logic for the dualpath fused floatingpoint addsubtract unit
 The data flow of a pipelined fused floatingpoint addsubtract unit
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SIMULATION VIDEO DEMO
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