A NEW ARCHITECTURE OF A TWO-STAGE LOSSLESS DATA COMPRESSION AND DECOMPRESSION ALGORITHM
Abstract—In this paper, we propose a new architecture for
the two-level lossless data compression and decompression algorithm
proposed that combines the PDLZW algorithm
and an approximated adaptive Huffman algorithm with dynamic-
block exchange (AHDB). In the new architecture, we
replace the CAM dictionary set used in the PDLZW algorithm
with a CAM-tag-based dictionary set to reduce hardware cost
and the CAM-based ordered list used in the AHDB algorithm
with a memory inter-reference (MIR) stage realized by using two
SRAMs. The resulting architecture is then implemented based
on cell-based libraries with both 0.35- m 2P4M and 0.18- m
1P6M process technologies, respectively. With the same process
technology, the prototyped chip demonstrates the new architecture
not only has better performance, at least 33% improvement, but
also occupies less area, only about 44%, and consumes less power,
about 50%, in comparison with the architecture proposed.
In addition, the maximum data rate can achieve 2 Gbps when
realizing in 0.35 m 2P4M process technology and 4 Gbps when
realizing in 0.18- m 1P6M process technology.
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THE CSI MULTIMEDIA ARCHITECTURE
MULTIMEDIA applications, such as audio and video compression/decompression and two-dimensional (2-D) and
three-dimensional (3-D) graphics ,provide new and highly valuable and appealing services to the consumer. Consequently , they
form a new important workload for the general - purpose workstation and desktop processors.General-purpose processors ,
however,are preferable to special-purpose media systems because they are easier to program,have higher performance growth,
and are less costly.Many microprocessor vendors have, therefore, extended their instruction set architecture(ISA)with instructions
targeted at multimedia applications.An instruction set extension designed to accelerate multimedia applications is evaluated. In
the proposed complex streamed instruction (CSI)set, a single instruction can process vector data streams of arbitrary length and
stride and combines complex memory accesses (with implicit prefetching ) , program control for vector sectioning, and complex
computations on multiple data in a single operation. In this way, CSI eliminates overhead instructions (such as instructions for
data sectioning, alignment, reorganization, and packing/unpacking) often needed in applications utilizing MMX-like extensions and
accelerates key multimedia kernels.
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