IMPLEMENTATION OF A MULTI-CHANNEL UART CONTROLLER BASED ON FIFO TECHNIQUE AND FPGA

     In several control systems, UART a kind of serial communication circuit is used widely. A universal asynchronous receive/ transmit (UART) is an integrated circuit which plays the most important role in serial communication. It handles the conversion the between serial and parallel data. Serial communication reduces the distortion of a signal, therefore makes data transfer between two systems separated in great distance possible.In some complex systems, communications between the master controller and slaver controllers are implemented by serial or parallel ort. Parallel communication needs a lot of multi-bit address bus and data bus and it is only convenient for short distance transmission. Serial communication is another way of communication used extensively because of its simple structure and long transmission distance. But sometimes a common serial port could not meet requirements of complex systems with different Baud Rates equipments even some special Baud Rate equipments. To meet modern complex control systems communication demands , the project presents a multi-channel UART controller based on FIFO(First In First Out) technique and FPGA(Field Programmable Gate Array).

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IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION

     When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check others are designed to detect as well as correct errors, such as Salomon Codes.However, the existing techniques are not able to achieve high efficiency & to meet bandwidth requirements, especially with the increase in the quantity of data transmitted. Orthogonal Code is one of the codes that can detect errors and correct corrupted data. This project is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.

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