VLSI ARCHITECTURE AND FPGA PROTOTYPING OF A DIGITAL CAMERA FOR IMAGE SECURITY AND AUTHENTICATION
WATERMARKING is the process that embeds data called a watermark, a tag, or label into a multimedia object such that
the watermark can be detected or extracted later to make an assertion about the object. The object may be an image,
audio, video, or text .In general, any watermarking scheme (algorithm) consists of three parts, such as the following:
1) Watermark;
2) Encoder (insertion algorithm);
3) Decoder and Comparator (verification or extraction or detection algorithm)
Watermarks and watermarking techniques can be divided into various categories, spatial domain and frequency domain.
According to human perception, the digital watermarks can be divided into four categories,
1) Visible;
2) Invisible-robust;
3) Invisible-fragile;
4) Dual
.
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A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE
Universal Asynchronous Receiver Transmitter (UART) based on Recursive Running Sum (RRS) filter. UARTs are used for
asynchronous serial data communication between remote embedded systems.The robust UART core used in this project ,
utilizes recursive running sum filter to remove noisy samples . Input data signal is directly sampled with system clock and
samples are accumulated over a window size . The window size is user programmable and it should be set to one third of
required bit period.
Universal Asynchronous Receiver Transmitter(UART)is used for asynchronous serial data communication between remote
embedded systems. Standard UART cores three mid -bit samples to decode the serial data bit and the sampling rate is
derived from external timer module.But if the physical channel is noisy then data bits get corrupted during transmission and
it leads to wrong data decoding at receiver.
To overcome the noise problem a digital low pass filter based architecture is proposed, Recursive Running Sum (RRS) is
simple low pass filter , it can be used to remove noise samples from data samples at receiver .Serial receive data signal is
directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable
and it decides baud rate. The robust UART core can be implemented on Xilinx/ALTERA FPGA devices.
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