16-BIT VEDIC DIVIDER

This project is design based on the paper "A Low Power 16 Bit Vedic Divider for High-Speed VLSI Applications". This project proposes the implementation of low power and high-speed Vedic Divider based on ancient Indian Vedic mathematics. In this project, an algorithm based on the “ParavartyaYojayet” is applied, throughout this sutra, the propagation delay and power consumption are reduced to an extent. As considered, the division operation is more complex in the computation of the digital applications. The most significant aspect of this paper is to reduce power consumption and provide high speed. In this work decimal and binary number, division algorithms are performed with filtering application to show the performance improvement of Paravartya Sutra over the normal divider. The project is developed using Verilog HDL with MatLab and simulation is performed using Modelsim/MatLab Software. Synthesis results are calculated using Xilinx ISE. The simulated results for proposed Vedic divider show a reduction in delay and power consumption against other division methods.

Division algorithm for decimal numbers is implemented based on “Paravartya-Yojayet – Transpose and Apply” see in table 1. The decimal division provides easier and logically simple implementation as illustrated using an example Paravartya Yojayet (Transpose and Apply).

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SIMULATION VIDEO DEMO

You can DOWNLOAD 8by4 Vedic divider Verilog HDL code and reference documents. Looking for full design contact us +91 7904568456 by WhatsApp or info@verilogcourseteam.com.

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