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This project is design based on the paper "High-Performance VLSI Architecture for 3-D Discrete Wavelet Transform". The architecture for 3-D DWT consisting of two parallel spatial processors (2-D DWT) and four temporal processors (1-D DWT). After applying 2-D DWT on two consecutive frames, each spatial processor (SP) produces 4 sub-bands, viz. LL, HL, LH, and HH which are fed to the inputs of four temporal processors (TPs) to perform the temporal transform. The output of these TPs consists of a low-frequency frame (L-frame) and a high-frequency frame (H-frame). The input image is converted into corresponding pixel values and stored in memory file i.e. text file using Matlab Programming, these input pixel values are given as input to DWT. The 3-D DWT is developed using Verilog HDL(Modelsim) as shown in the below diagram. The output generated pixel using 3-D DWT is converted into image format using Matlab Program. Watch the simulation video demo for design working process.
Block diagram of a 3-D discrete wavelet transform
Request source code for academic purpose REQUEST FORM
SIMULATION VIDEO DEMO
You can DOWNLOAD the sample code for DWT Stage-1 and 2.Need design files, contact info@verilogcourseteam.com or WhatsApp @ +91 7904568456, fee applicable.
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