Embedded Files
This project is design based on the paper "Hardware-Software Co-Simulation of Edge Detection for Image Processing".The Image edge detection design is divided into two major parts, Hardware and Software. The Hardware implementation uses a Digilent Nexys2 Board with Spartan 3E FPGA. On the software side, Matlab is responsible for transferring images to pixel values. The project was developed using a hierarchical structure. The top-level structure includes the following major units:
Image to Pixel Values Conversion using Matlab
Edge Detection Algorithm using Verilog HDL
Pixel Values to Edge Detected Image using Matlab
VGA Display module using VHDL
Memory Controller to store Pixel values using VHDL
The memory controller and VGA module are designed for the Nexys2 board which available from Digilent Website. The detailed procedure for Simulation and FPGA Implementation is given below,
The input image is converted into corresponding values using the Matlab program.
These values are stored in files and passed to Canny Edge detection design through test bench.
The pixel stored values called using $readmemh or $readmemb with the external file name.
Edges are found in the image using Verilog HDL with Modelsim software and final image value is stored in another file.
By using the Matlab program the edge detected images values are converted into Image.
This level is up to the simulation process.
To implement in FPGA the interface coding to be written for VGA display.
First, the Edge detected image values to be stored in external memory (RAM) in VGA interface coding.
Then the VGA module is synthesized and implemented to the target device.
The interface coding will differ depends on Technology or Device family.
In this demo, we used Spartan 3E xc3s500e.
Create the bit file and specify the pin location in UCF file.
Connect the USB and monitor cable properly.
Check the cable set up and get device id.
Finally, program it and you can get the image output in an external monitor.
Request source code for academic purpose REQUEST FORM
SIMULATION VIDEO DEMO
FPGA IMPLEMENTATION DEMO
You can DOWNLOAD Canny Edge Detection Verilog HDL code and reference papers. Looking for design files, contact +91 7904568456 by WhatsApp or info@verilogcourseteam.com, fee applicable.
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