Embedded Files
This project is design based on the paper "Improved Architectures for a Fused Floating-Point Add-Subtract Unit".The fused floating-point add-subtract unit is useful for digital signal processing (DSP) applications such as fast Fourier transform (FFT) and discrete cosine transform (DCT) butterfly operations. To improve the performance of the fused floating-point add-subtract unit, a dual-path algorithm and pipelining are employed. The proposed designs are implemented for both single and double precision. This project is designed using Verilog HDL and simulated using Modelsim for the below methods.
Fused floating-point add-subtract unit
Dual-path fused floating-point add-subtract unit
Fused floating-point add-subtract unit (after Close path logic for the dual-path fused floating-point add-subtract unit
The data flow of a pipelined fused floating-point add-subtract unit
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SIMULATION VIDEO DEMO
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