DESIGN OF FULL-RATE IEEE 802.11A BASEBAND PROCESSOR
With the rapid growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on the OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data-rate requirements of 802.11a standard. Although software-based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by Matlab software. The block diagram of a digital baseband transmitter defined in the 802.11a standard is shown in below figure. The input bit-stream is first randomized by a scrambler and encoded by a convolutional encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit-stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. BPSK, QPSK and QAM modulation schemes are used in the design. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time-domain signals. Finally, the resulting time-domain signals are cyclically extended to form the guard interval for each OFDM symbol. Watch the simulation video demo for the design working process.
Reference Paper-1: Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
Author’s Name: Yiyan Tang, Lie Qian, and Yuke Wang
Source: IEEE Globecom
Year: 2005
Reference Paper-2: Implementation of IEEE 802.11 a WLAN Baseband Processor
Author’s Name: Je-Hoon Lee, Young-Il Lim, and Kyoung-Rok Cho
Source: IEEE
Year: 2007
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SIMULATION VIDEO DEMO
