DCT AND IDCT ARCHITECTURE USING VERILOG HDL WITH MATLAB
The Discrete Cosine transform is widely used as the core of digital image compression. Discrete cosine transforms attempt to de-correlate the image data. After decorrelation, each transform coefficient can be encoded independently without losing compression efficiency. This design is based on 8x8 2D DCT/IDCT. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two 1-D DCT calculations by using a transpose buffer. To verify the algorithm, we used Verilog HDL with Matlab program. The simulation is carried out using Matlab along with Modelsim software where the input image is converted into corresponding pixel values using Matlab then those values are processed using image reconstruction algorithm in Verilog HDL.
REFERENCES
Reference Paper-1: VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for JPEG
Author’s Name: Subramanian P, A Sagar Chaitanya Reddy
Source: IEEE
Year: 2010
You can DOWNLOAD the Verilog HDL code to execute the design.
SIMULATION VIDEO DEMO
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