IMAGE FEATURE EXTRACTION USING VERILOG HDL WITH MATLAB
This design is based on image feature extraction process which involves faster scanning the image with windows (sub-images) of a given dimension and a given scanning step. This step corresponds to the offset between two consecutive sub-images. The architecture consists of two stages, a pre-processing stage, and the feature extraction block. The first prepares input data to be processed by the feature extraction block while the second combines both software and hardware to calculate GLCM features. The performance of the feature extraction scheme is evaluated using Matlab software along Modelsim for Simulation.
REFERENCES
Reference Paper-1: An FPGA-based Architecture for Real Time Image Feature Extraction
Author’s Name: D.G. Bariamis, D.K. Iakovidis, D.E. Maroulis and S. A. Karkanis
Source: IEEE
Year: 2004
You can DOWNLOAD the Verilog HDL code to execute the design.
SIMULATION VIDEO DEMO
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