VLSI

Standard Training Model - VLSI

Digital Systems

  • Boolean algebra.

  • Combinational / sequential circuits.

  • K-map simplification.

    • Flip flop and latches.

    • State machines.

    • Counters and shift registers.

  • Case studies.

Verilog HDL Programming

  • Introduction to HDL.

  • Verilog modeling concepts.

  • Verilog HDL conventions.

  • Data types in verilog.

  • Gate level modeling.

    • Operators.

    • Continuous assignments.

    • Behavioral modeling.

    • Compiler directives.

    • Tasks and functions.

    • Test benches-basics.

    • Assignments.

    • Writing verilog models.

VHDL Programming

  • Introduction.

    • Levels of representation and abstraction.

  • Basic structure of a VHDL file.

    • Behavioral model.

    • Concurrency.

    • Structural description.

  • Lexical elements of VHDL.

    • Data objects: signals, variables and constants.

    • Variable.

    • Signal.

    • Data types.

  • Integer types.

    • Attributes.

  • Operators.

  • Behavioral modeling: sequential statements.

    • Looping statement.

    • Test environment.

    • Data flow modeling – concurrent statements.

  • Structural modeling.

FPGA Synthesis

  • Working process with synthesis tool.

  • Setting constraints.

  • Timing analysis - introduction.

FPGA Implementation

  • Implementation procedures.

  • Setting target device.

  • Device programming using ALTERA / XILINX.

System Verilog

  • Introduction.

    • History of verilog HDL.

    • What is system verilog.

      • System verilog verification environment.

    • Language overview.

        • 2001 structures.

        • Data types.

        • Array.

        • Struct / union.

        • Module and interface.

        • Operators.

        • Event scheduling in system verilog program.

    • System verilog classes.

    • Random constraints.

    • System verilog assertions.

    • Functional coverage.

    • System tasks and functions.

    • VMM tutorial.

    • OVM tutorial.

ASIC Synthesis

    • ASIC synthesis-materials.

    • Working process with synthesis tool.

    • Setting technology-libraries.

    • Setting constraints.

    • Introduction to shell and TCL scripting.

EDA Simulation Tools

    • Active HDL

    • Mentor graphics- Modelsim / Questasim.

    • Synopsys - VCS.

    • Cadence - NC verilog / verilog XL.

    • Riviera Pro

EDA Synthesis Tools

    • Xilinx - Xilinx ISE.

    • Altera - Quartus II.

Project Planning / Management

    • Design specification analysis.

    • Directory structure.

    • Test plan.

    • Test environment.

    • RTL - coding guidelines.

    • Documentation.

Real Time- Industry Standard Project

    • AMBA.

    • PCI EXPRESS.

    • USB.