USB TRANSCEIVER MACROCELL INTERFACE WITH USB2.0
This project is design based on the paper "FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications". Universal Serial Bus(USB)Transceiver Macrocell Interface (UTMI) is a two-wire, bi-directional serial bus interface. The USB2.0 specifications define three types of UTMI implementations depends on data transmission rates, those are Low Speed (1.5MHz) only (LS), Full Speed (12MHz) only (FS) and High Speed (480MHz)/Full speed (12MHz) (HS). UTMI consists of two main blocks, Transmitter and Receiver.
Block diagram of UTMI
The transmitter module has been implemented by considering the following specifications.
The SYNC pattern “01111110” has to be transmitted immediately after the transmitter is initiated by the SIE.
After six consecutive ‘1’s occur in the data stream a zero to be inserted.
The data should be encoded using Non-Return to Zero Invert on 1 (NRZI -1) encoding technique.
The EOP pattern two single-ended zeroes(D+ and Dlines are carrying zero for two clock cycles) and a bit one have to be transmitted after each packet or after SIE suspends the transmitter
The receiver module has been implemented by considering the following specifications.
When SYNC pattern is detected that should be intimated to the SIE.
If zero is not detected after six consecutive ‘1’s an error should be reported to the SIE.
When EOP pattern is detected that should be intimated to the SIE. The receiver logic facilitates SYNC detection, NRZI decoding, bit unstuffing, serial to parallel conversion of data, receive error reporting and EOP detection.
Request source code for academic purpose REQUEST FORM
SIMULATION VIDEO DEMO
You can DOWNLOAD Transmitter Verilog HDL code and reference documents. Looking for full design contact us +91 7904568456 by WhatsApp or info@verilogcourseteam.com.