LIFTING BASED 2 D DISCRETE WAVELET TRANSFORM FOR DUAL SCAN PARALLEL FLIPPING ARCHITECTURE
The conventional 9/7 lifting has two lifting steps and one scaling step. The DFG where d0 i+2 and s0 i+2 are the input data of the current cycle, and d2i and s2i are the outputs of the current cycle obtained using intermediate data d0 i+1, s0 i+1, d1i, s1i, and d2i−1 from the internal memory devices. The conventional lifting scheme serially processes these intermediate data, resulting in a longer critical path. Therefore, in the proposed algorithm, the DFG is modified to process the intermediate data in advance to shorten the critical. The dual-scan parallel flipping architecture (DSPFA) is derived from the proposed modified DFG. Odd and even inputs are accessed in a Z-scan fashion, in which the numbers indicate the order in which pixels are read on the rising edge of the clock. The entire image is segmented into a tile of 2 × 2 pixels so that the column processing can start as soon a 1-D DWT is generated by alternate row processing. Z-scanning allows simultaneous row and column processing operation, resulting in a small fixed latency and transposing buffer size that is independent of N. The modified 2D-DWT algorithm is developed using Verilog HDL and Matlab is used to convert image input into values.
DFG of the Modified Algorithm
Reference Paper: Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform
Author's Name: Anand Darji, Shubham Agrawal, Ankit Oza, Vipul Sinha, Aditya Verma, S. N. Merchant, and A. N. Chandorkar
Source: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS
Year:2014
Request source code for academic purpose REQUEST FORM or contact +91 7904568456 by WhatsApp or info@verilogcourseteam.com, fee applicable.
SIMULATION VIDEO DEMO
